1. Field of the Invention
This invention relates to a circuit for sampling repeatable information signals where the sampling point on the signal is controllably varied by means of a controlled variable delay line to provide sampling at different points along the signal wave after plural successive samplings thereof.
2. Brief Description of the Prior Art
It is often necessary to sample signals at a sampling rate higher than the capability of the available equipment. Such problems often occur due to limitations in the art or for reasons of economics where the equipment having the desired capability is not an economically viable alternative. In the prior art, it has normally been necessary to either utilize the economically unfeasible equipment or, alternatively, to use reduced capability equipment with the inherent inferior results. In either case, there is a tradeoff required in order to provide the high sampling rate required. In one case there is an economic penalty and in the other case there is a resolution penalty. For this reason, where cost is a significant factor, it often becomes economically unfeasible to provide the required sampling rates in converting an analog to a digital signal.
One attempt to overcome this problem is provided in U.S. Pat. No. 4,595,908 of James H. Gordon. In this circuit, a relatively inexpensive, relatively slow sampling rate A-D converter is used to provide results which approach those of higher sampling rate converters. A trigger signal is generated, which signal is provided as an output to trigger the occurrence of an event. The event has associated therewith an analog signal which is synchronous with the trigger signal. Also synchronous with the trigger and analog signals is the digitization of the analog signal by the analog to digital converter. There is a memory buffer that is filled with the digitized waveform at a fixed sampling rate. Both the analog to digital converter and the address counter for the memory buffer are clocked by a fixed frequency, continuously running clock. For example, at a sampling rate of 25 MHz. the analog signal is sampled every 40 ns, converted to a digital value and stored in the memory buffer. If the memory buffer is 1024 bytes in length, the circuit continues to digitize and store the values until the memory buffer is full.
The delay circuit is inserted in series with the trigger out signal. The trigger out signal will be delayed with respect to the digitization and storing process. For example, the delay circuit is digitally controlled and can be made to delay the trigger signal in 5 ns increments from 0 ns to 35 ns in eight steps. If the analog signal is synchronous and repeatable with respect to the trigger out signal, then the analog signal may be equivalently sampled at 200 MHz using the delay line in this example. Eight triggers must be issued, each with a different delay inserted. If the memory buffer is 1024 bytes in length, for example, then eight buffers are accumulated containing the same waveform. The digitized points on the waveforms are offset in time by 5 ns. When the eight buffers are interleaved and combined to form one buffer that is 8192 bytes in length, this new buffer now represents the digitized waveform equivalently sampled every 5 ns or at a sampling rate of 200 MHz.
The deficiency of this method is that the circuit must be in control of the analog signal. That is, it must provide a trigger out signal that will cause a synchronous, repeatable analog signal to be generated by a slaved external event. This method cannot digitize free running repetitive signals, even if there is a synchronous trigger signal provided with the analog signal. The problem is that the analog signal, though repeatable, is occurring asynchronously with respect to the free running clock used by the analog to digital converter.